View APW714509_4897725.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

APW7145
3A, 12V, Synchronous-Rectified Buck Converter
Features
* * * * * *
Wide Input Voltage from 4.3V to 14V Output Current up to 3A Adjustable Output Voltage from 0.8V to VIN - 2% System Accuracy 55m Integrated Power MOSFETs High Efficiency up to 95% - Automatic Skip/PWM Mode Operation Current-Mode Operation - Easy Feedback Compensation - Stable with Low ESR Output Capacitors - Fast Load/Line Transient Response
General Description
The APW7145 is a 3A synchronous-rectified Buck converter with integrated 55m power MOSFETs. The APW7145, designed with a current-mode control scheme, can convert wide input voltage of 4.3V to 14V to the output voltage adjustable from 0.8V to VIN to provide excellent output voltage regulation. For high efficiency over all load current range, the APW7145 is equipped with an automatic Skip/PWM mode operation. At light load, the IC operates in the Skip mode, which keeps a constant minimum inductor peak current, to reduce switching losses. At heavy load, the IC works in PWM mode, which inductor peak current is programmed by the COMP voltage, to provide high efficiency and excellent output voltage regulation. The APW7145 is also equipped with power-on-reset, softstart, soft-stop, and whole protections (under-voltage, over-voltage, over-temperature, and current-limit) into a single package. In shutdown mode, the supply current drops below 3A. This device, available SOP-8P and DFN4x4-8 packages, provides a very compact system solution with minimal external components and PCB area.
* * * * * * * * * *
Power-On-Reset Monitoring Fixed 500kHz Switching Frequency in PWM Mode Built-In Digital Soft-Start and Soft-Stop Current-Limit Protection with Frequency Foldback 123% Over-Voltage Protection Hiccup-Mode 50% Under-Voltage Protection Over-Temperature Protection <3A Quiescent Current in Shutdown Mode SOP-8P and Compact 4mmx4mm DFN-8 (DFN4x4-8) Packages Lead Free and Green Devices Available (RoHS Compliant)
100 90 80 70 60 50 40 30 20 10 0 0.001
VIN=12V, VOUT=2V, L1=3.3H VIN=5V, VOUT=3.3V, L1=2.2H VIN=12V, VOUT=5V, L1=6.8H VIN=12V, VOUT=3.3V, L1=4.7H VIN=5V, VOUT=1.2V, L1=2.2H
Applications
* * * *
OLPC, UMPC Notebook Computer Handheld Portable Device Step-Down Converters Requiring High Efficiency and 3A Output Current
0.01
0.1
1
10
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009 1 www.anpec.com.tw
APW7145
Pin Configuration
APW7145 NC VIN AGND FB 1 2 3 4 8 7 6 5 PGND LX EN COMP
NC VIN AGND FB APW7145 1 2 3 4 8 7 6 5 PGND LX EN COMP
9
LX
SOP-8P Top View
DFN 4x4-8 Top View
The Pin 7 must be connected to the Exposed Pad
Ordering and Marking Information
APW7145 Assembly Material Handling Code Temperature Range Package Code Package Code KA : SOP-8P QA: DFN4x4-8 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device
APW7145 KA :
APW7145 XXXXX
XXXXX - Date Code
APW7145 QA :
APW7145 XXXXX
XXXXX - Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight).
Absolute Maximum Ratings
Symbol VIN VLX VIN Supply Voltage (VIN to AGND) LX to GND Voltage PGND to AGND Voltage EN to AGND Voltage FB, COMP to AGND Voltage PD TSTG TSDR Power Dissipation Maximum Junction Temperature Storage Temperature
(Note 1)
Rating -0.3 ~ 15 > 100ns < 100ns -1 ~ VIN+1 - 5 ~ VIN+5 -0.3 ~ +0.3 -0.3 ~ VIN+0.3 -0.3 ~ 6 Internally Limited 150 -65 ~ 150 260 Unit V V V V V W
o o o
Parameter
C
C C
Maximum Lead Soldering Temperature, 10 Seconds
Note 1 : Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device.
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
2
www.anpec.com.tw
APW7145
Thermal Characteristics
Symbol JA Junction-to-Case Resistance in Free Air (Note 3) JC SOP-8P DFN4x4-8 20 30
o
Parameter Junction-to-Ambient Thermal Resistance in Free Air (Note 2) SOP-8P DFN4x4-8
Typical Value 50 65
Unit
o
C/W
C/W
Note 2: JA is measured with the component mounted on a high effective thermal conductivity test board in free air. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P and DFN4x4-8 packages.
Recommended Operating Conditions (Note 4)
Symbol VIN VOUT IOUT CIN COUT LOUT VIN Supply Voltage Converter Output Voltage Converter Output Current Converter Input Capacitor (MLCC) Converter Output Capacitor Effective Series Resistance Converter Output Inductor Resistance of the Feedback Resistor connected from FB to GND TA TJ Ambient Temperature Junction Temperature Parameter Range 4.3 ~ 14 0.8 ~ VIN 0~3 8 ~ 50 20 ~ 1000 0 ~ 60 1 ~ 22 1 ~ 20 -40 ~ 85 -40 ~ 125 Unit V V A F F m H k
o o
C C
Note 4: Refer to the Typical Application Circuits
Electrical Characteristics
Refer to the "Typical Application Circuits". These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85C, unless otherwise specified. Typical values are at TA=25C. Symbol SUPPLY CURRENT IVIN IVIN_SD VIN Supply Current VIN Shutdown Supply Current VFB = VREF +50mV, VEN=3V, LX=NC VEN = 0V VIN rising 0.5 1.5 3 mA A V V Parameter Test Conditions Min. APW7145 Typ. Max. Unit
POWER-ON-RESET (POR) VOLTAGE THRESHOLD VIN POR Voltage Threshold VIN POR Hysteresis REFERENCE VOLTAGE VREF Reference Voltage Output Voltage Accuracy Line Regulation Load Regulation Regulated on FB pin TJ = 25oC, IOUT=10mA, VIN=12V IOUT=10mA~3A, VIN=4.75~14V VIN = 4.75V to 14V IOUT = 0.5A ~ 3A -1.0 -2.0 0.8 +0.02 -0.04 +1.0 +2.0 V % %/V %/A 3.9 4.1 0.5 4.3 -
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
3
www.anpec.com.tw
APW7145
Electrical Characteristics (Cont.)
Refer to the "Typical Application Circuits". These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85C, unless otherwise specified. Typical values are at TA=25C. Symbol Parameter Test Conditions Min. OSCILLATOR AND DUTY CYCLE FOSC Oscillator Frequency Foldback Frequency Maximum Converter' Duty s TON_MIN Minimum Pulse Width of LX TJ = -40 ~ 125oC, VIN = 4.75 ~ 14V VOUT = 0V 450 500 80 99 150 550 kHz kHz % ns A/V dB V/A APW7145 Typ. Max. Unit
CURRENT-MODE PWM CONVERTER Gm Error Amplifier Transconductance Error Amplifier DC Gain Current-Sense to COMP Voltage Transresistance Between VIN and Exposed Pad, VIN = 5V, TJ=25C Between VIN and Exposed Pad, VIN = 12V, TJ=25C Between GND and Exposed Pad, VIN = 5V, TJ=25C Between GND and Exposed Pad, VIN = 12V, TJ=25C Peak Current VFB falling VFB rising VFB=VREF50mV COMP = NC 200 80 0.1 70 55 55 45 100 m 80 100 m 80
High-Side Switch Resistance
Low-Side Switch Resistance
PROTECTIONS ILIM VTH_UV VTH_OV High-Side Switch Current-limit FB Under-Voltage Threshold FB Over-Voltage Threshold FB Under-Voltage Debounce TOTP Over-Temperature Trip Point Over-Temperature Hysteresis TD Dead-Time VLX = -0.7V 5 45 118 6.5 50 123 1 150 40 20 8 55 128 A % % s
o
C C
o
ns
SOFT-START, SOFT-STOP, ENABLE, AND INPUT CURRENTS TSS Soft-Start / Soft-Stop Interval EN Shutdown Voltage Threshold EN Enable Voltage Threshold High-side Switch Leakage Current IFB IEN FB Pin Input Current EN Pin Input Current VEN = 0V ~ VIN VEN = 0V, VLX = 0V VEN falling 1.5 0.5 -100 -100 2 2.5 2.1 2 +100 +100 ms V V A nA nA
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
4
www.anpec.com.tw
APW7145
Typical Operating Characteristics
(Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=4.7H) Output Current vs. Efficiency
100 90
Output Voltage, VOUT (V) Efficiency (%)
3.4 3.38 3.36 3.34 3.32 3.3 3.28 3.26 3.24
VIN=12V, VOUT=2V, L1=3.3H
Output Current vs. Output Voltage
80 70 60 50 40 30 20 10 0 0.001
VIN=5V, VOUT=3.3V, L1=2.2H VIN=12V, VOUT=5V, L1=6.8H VIN=12V, VOUT=3.3V, L1=4.7H VIN=5V, VOUT=1.2V, L1=2.2H
3.22 3.2
0.01
0.1
1
10
0
1
2
3
Output Current, IOUT(A)
Output Current, IOUT(A)
Current Limit Level (Peak Current)
7
Output Voltage vs. Supply Voltage
3.4 3.38
vs. Junction Temperature
Current Limit Level, ILIM(A)
IOUT=500mA
7.5
Output Voltage, VOUT (V)
-40 -20 0 20 40 60 80 100 120 140
3.36 3.34 3.32 3.3 3.28 3.26 3.24 3.22
7
6.5
6
5.5
3.2 4 6 8 10 12 14
Junction Temperature, TJ (oC)
Supply Voltage, VIN (V)
VIN Input Current vs. Supply Voltage
2.0
Reference Voltage vs. Junction Temperature
0.816 0.812
VFB=0.85V
VIN Input Current, IVIN(mA)
1.5
Reference Voltage, VREF (V)
0.808 0.804 0.800 0.796 0.792 0.788 0.784 -50
1.0
0.5
0.0 0 2 4 6 8 10 12 14
-25
0
25
50
75
100
o
125
150
Supply Voltage, VIN (V) Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009 5
Junction Temperature, TJ ( C) www.anpec.com.tw
APW7145
Typical Operating Characteristics (Cont.)
(Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=4.7H) Oscillator Frequency vs. Junction Temperature
550 540 530 520 510 500 490 480 470 460 450 -50 -25 0 25 50 75 100
o
Oscillator Frequency, FOSC(KHz)
125
150
Junction Temperature, TJ ( C)
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
6
www.anpec.com.tw
APW7145
Operating Waveforms
(Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=4.7H)
Power On
Power Off
IOUT=3A VIN 1
IOUT=3A VIN 1 VOUT 2 IL1 3 CH1 : VIN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1 , 2A/div Time : 1ms/div
VOUT 2 IL1 3
CH1 : VIN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1 , 2A/div Time : 10ms/div
Enable
IOUT=3A
IOUT=3A
Shutdown
1
VEN
VEN 1
VOUT 2 IL1 3
3 2
VOUT
IL1
CH1 : VEN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1 , 2A/div Time : 1ms/div
CH1 : VEN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1, 2A/div Time : 100s/div
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
7
www.anpec.com.tw
APW7145
Operating Waveforms (Cont.)
(Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=4.7H) Short Current
IOUT =3~7A 1 VLx
VLX 1
Short Circuit
VOUT is shorted to GND by a short wire
VOUT
2
VOUT
2 3 IL1
3 IL1
CH1 : VLX , 10V/div CH2 : VOUT , 2V/div CH3 : IL1 , 5A/div Time : 20s/div
CH1 : VLX , 5V/div CH2 : VOUT , 200mV/div CH3 : IL1 , 5A/div Time : 5ms/div
Load Transient Response
IOUT= 50mA-> 3A ->50mA IOUT rising/falling time=10s VOUT
Load Transient Response
IOUT= 0.5A-> 3A ->0.5A IOUT rising/falling time=10s 1 VOUT
1
IL1
IL1
2
2
CH1 : VOUT , 200mV/div CH2 : IL1 , 2A/div Time : 100s/div
CH1 : VOUT , 100mV/div CH2 : IL1 , 2A/div Time : 100s/div
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
8
www.anpec.com.tw
APW7145
Operating Waveforms (Cont.)
(Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=4.7H) Switching Waveform
IOUT=0.2A VLX
Switching Waveform
VLX
IOUT=3A
1
1 IL1
IL1 2
2
CH1 : VLX , 5V/div CH2 : IL1 , 2A/div Time : 1s/div
CH1 : VLX , 5V/div CH2 : IL1 , 2A/div Time : 1s/div
Line Transient
VIN= 5~12V VIN VIN rising/falling time=20s
VIN
Over Voltage Protection
VOUT
1 VOUT 2 IL1
1 2 3 4 IL1 VLX
3
IOUT=-1A
CH1 : VIN , 5V/div CH2 : VOUT , 50mV/div (Voffset=3.3V) CH3 : IL1 , 2A/div Time : 100s/div
CH1 : VIN , 5V/div CH2 : VOUT , 2V/div CH3 : VLX , 5V/div CH4 : IL1 , 5A/div Time : 20s/div
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
9
www.anpec.com.tw
APW7145
Pin Description
PIN NO. 1 2 3 4 NAME NC VIN AGND FB No Connection. Power Input. VIN supplies the power (4.3V to 14V) to the control circuitry, gate drivers and step-down converter switches. Connecting a ceramic bypass capacitor and a suitably large capacitor between VIN and both of AGND and PGND to eliminate switching noise and voltage ripple on the input to the IC. Ground of MOSFET Gate Drivers and Control Circuitry. Output Feedback Input. The APW7145 senses the feedback voltage via FB and regulates the voltage at 0.8V. Connecting FB with a resistor-divider from the converter' s output sets the output voltage from 0.8V to VIN. Output of the error amplifier. Connecting a series RC network from COMP to GND to compensate the regulation control loop. In some cases, an additional capacitor from COMP to GND is required. Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive it low to turn it off. Connecting this pin to VIN if it is not used. Power Switching Output. LX is the junction of the high-side and low-side power MOSFETs to supply power to the output LC filter. Power Ground of the APW7145, which is the source of the N-channel power MOSFET. Connect this pin to the system ground with lowest impedance. Power Switching Output. LX is the Drain of the P-channel MOSFET to supply power to the output. The Exposed Pad provides current with lower impedance than the Pin 7. Connecting the pad to output LC filter via a top-layer thermal pad on PCBs. The PCB will be a heat sink of the IC. FUNCTION
5 6 7 8 9 (Exposed Pad)
COMP EN LX PGND
LX
Block Diagram
VIN
Current Sense Amplifier Power-OnReset Current Limit Zero-Crossing Comparator
VIN
POR OVP 123%VREF 50%VREF UVP Soft-Start / Soft-Stop
UG Soft-Start / Soft-Stop and Fault Logic Inhibit Gate Control VIN LG Current Compartor Slope Compensation Gate Driver Gate Driver
LX
FB
VREF
Gm Error Amplifier
COMP
PGND
EN
1.5V
Enable
OverTemperature Protection
FB
Oscillator 500kHz
AGND
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
10
www.anpec.com.tw
APW7145
Typical Application Circuit
1. 4.3~14V Single Power Input Step-down Converter (with a Ceramic Output Capacitor)
VIN
2 VIN Enable 6 Shutdown EN LX 9 7 8
C1 L1 3A
VOUT
C2 R1 O % 1
U1 LX APW7145
PGND 5 COMP FB AGND 3
R3 (O %) 5 C3 (O 0%) 3
4
R2 O % 1
C4 (O 0%, Optional) 3
a. Cost-effective Feedback Compensation (C4 is no connection)
V IN(V) V OUT(V) L1(F) C2(F) C2 ESR(m) R1(k) R2(k) R3(k) C3(pF)
12 12 12 12 12 12 12 12 5 5 5 5 5 5 5 5
5 5 3.3 3.3 2 2 1.8 1.8 3.3 3.3 1.8 1.8 1.5 1.5 1.2 1.2
6.8 6.8 4.7 4.7 3.3 3.3 3.3 3.3 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2
22 44 22 44 22 44 22 44 22 44 22 44 22 44 22 44
5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3
63.0 63.0 46.9 46.9 30.0 30.0 18.8 18.8 46.9 46.9 25.0 25.0 21.9 21.9 7.5 7.5
12 12 15 15 20 20 15 15 15 15 20 20 25 25 15 15
33.0 68.0 27.0 56.0 18.0 33.0 15.0 30.0 27.0 56.0 15.0 30.0 12.0 24.0 10.0 20.0
820 820 1000 1000 1800 1800 1800 1800 470 470 820 820 1000 1000 1200 1200
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
11
www.anpec.com.tw
APW7145
Typical Application Circuit (Cont.)
b. Fast-Transient-Response Feedback Compensation (C4 is connected) VIN(V) 12 12 12 12 12 12 12 12 5 5 5 5 5 5 5 5 VOUT(V) 5 5 3.3 3.3 2 2 1.8 1.8 3.3 3.3 1.8 1.8 1.5 1.5 1.2 1.2 L1(H) 6.8 6.8 4.7 4.7 3.3 3.3 3.3 3.3 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 C2(F) 22 44 22 44 22 44 22 44 22 44 22 44 22 44 22 44 C2 ESR(m) 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 R1(k) 63.0 63.0 46.9 46.9 30.0 30.0 18.8 18.8 46.9 46.9 25.0 25.0 22 22 7.5 7.5 R2(k) 12 12 15 15 20 20 15 15 15 15 20 20 25 25 15 15 R3(k) 43 82 27 56 18 33 15 30 27 56 15 30 12 24 10 20 C3(pF) 680.0 680.0 1000.0 1000.0 1800.0 1800.0 1800.0 1800.0 470.0 470.0 820.0 820.0 1000 1000 1200 1200 C4(pF) 27 27 27 27 27 27 33 33 27 27 56 56 56 56 180 270
2. +12V Single Power Input Step-down Converter (with an Electrolytic Output Capacitor)
C1
2 VIN Enable 6 Shutdown EN LX 9 7 8
2.2F
C5 470F L1
VIN 12V
4.7H /3A
U1 LX APW7145
PGND 5 COMP FB AGND 3 4
VOUT 3.3V/3A
C2 470F (ESR=30m)
R3 100K C3 1000pF
R1 46.9K 1%
R2 15K 1%
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
12
www.anpec.com.tw
APW7145
Function Description
VIN Power-On-Reset (POR) The APW7145 keeps monitoring the voltage on the VIN pin to prevent wrong logic operations which may occur when VIN voltage is not high enough for the internal control circuitry to operate. The VIN POR has a rising threshold of 4.1V (typical) with 0.5V of hysteresis. During start-up, the VIN voltage must exceed the enable voltage threshold. Then, the IC starts a start-up process and ramps up the output voltage to the voltage target. Digital Soft-Start The APW7145 has a built-in digital soft-start to control the rise rate of the output voltage and limit the input current surge during start-up. During soft-start, an internal voltage ramp (VRAMP), connected to one of the positive inputs of the error amplifier, rises up from 0V to 0.95V to replace the reference voltage (0.8V) until the voltage ramp reaches the reference voltage. During soft-start without output over-voltage, the APW7145 converter' sinking capability is disabled until the output s voltage reaches the voltage target. Digital Soft-Stop At the moment of shutdown controlled by EN signal, under-voltage event, or over-temperature protection, the APW7145 initiates a digital soft-stop process to discharge the output voltage in the output capacitors. Certainly, the load current also discharges the output voltage. During soft-stop, the internal voltage ramp (VRAMP) falls down from 0.95V to 0V to replace the reference voltage. Therefore, the output voltage falls down slowly at light load. After the soft-stop interval elapses, the soft-stop process ends and the the IC turns on the low-side power MOSFET. Output Undervoltage Protection (UVP) In the operational process, if a short-circuit occurs, the output voltage will drop quickly. Before the current-limit circuit responds, the output voltage will fall out of the required regulation range. The undervoltage continually monitors the FB voltage after soft-start is completed. If a load step is strong enough to pull the output voltage lower than the under-voltage threshold, the IC shuts down converter' output. s The under-voltage threshold is 50% of the nominal output voltage. The undervoltage comparator has a built-in 2s noise filter to prevent the chips from wrong UVP shutdown caused by noise. The under-voltage protection works in a hiccup mode without latched shutdown. The IC will initiate a new soft-start process at the end of the preceding delay. Over-Voltage Protection (OVP) The over-voltage function monitors the output voltage by FB pin. When the FB voltage increase over 123% of the reference voltage due to the high-side MOSFET failure, or for other reasons, the over-voltage protection comparator will force the low-side MOSFET gate driver high. This action actively pulls down the output voltage and eventually attempts to blow the internal bonding wires. As soon as the output voltage is within regulation, the OVP comparator is disengaged. The chip will restore its normal operation. This OVP scheme only clamps the voltage overshoot and does not invert the output voltage when otherwise activated with a continuously high output from lowside MOSFET driver - a common problem for OVP schemes with a latch. Over-Temperature Protection (OTP) The over-temperature circuit limits the junction temperature of the APW7145. When the junction temperature exceeds TJ = +150oC, a thermal sensor turns off the both power MOSFETs, allowing the devices to cool. The thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 40 oC. The OTP is designed with a 40 oC hysteresis to lower the average TJ during continuous thermal overload conditions, increasing lifetime of the APW7145. Enable/Shutdown Driving EN to the ground initiates a soft-stop process and then places the APW7145 in shutdown. When in shutdown, after the soft-stop process is completed, the internal power MOSFETs turns off, all internal circuitry shuts down and the quiescent supply current reduces to less than 3mA.
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
13
www.anpec.com.tw
APW7145
Function Description (Cont.)
Current-Limit Protection The APW7145 monitors the output current, flowing through the high-side power MOSFET, and limits the current peak at current-limit level to prevent loads and the IC from damages during overload or short-circuit conditions. Frequency Foldback The foldback frequency is controlled by the FB voltage. When the output is shortened to the ground, the frequency of the oscillator will be reduced to 80kHz. This lower frequency allows the inductor current to safely discharge, thereby preventing current runaway. The oscillator' fres quency will gradually increase to its designed rate when the feedback voltage on FB again approaches 0.8V.
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
14
www.anpec.com.tw
APW7145
Application Information
Setting Output Voltage The regulated output voltage is determined by:
VOUT = 0.8 (1 + R1 ) R2
T=1/FOSC
VLX
(V)
DT
I
IOUT
Suggested R2 is in the range from 1K to 20k. For portable applications, a 10K resistor is suggested for R2. To prevent stray pickup, please locate resistors R1 and R2 close to APW7145. Input Capacitor Selection Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge current needed each time the P-channel power MOSFET (Q1) turns on. Place the small ceramic capacitors physically close to the VIN and between the VIN and the GND. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current (IRMS) of the bulk input capacitor is calculated as the following equation:
IL IOUT IQ1 I ICOUT
VOUT
VOUT
Figure 1. Converter Waveforms
Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are the function of the switching frequency and the ripple current (I). The output ripple is the sum of the voltages, having phase shift, across the ESR, and the ideal output capacitor. The peak-to-peak voltage of the ESR is calculated as the following equations:
D= I = VOUT VIN VOUT *(1 - D) FOSC *L
........... (1) ........... (2) ........... (3)
IRMS = IOUT D (1- D)
(A)
where D is the duty cycle of the power MOSFET. For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating.
VIN CIN
VESR = I. ESR
The peak-to-peak voltage of the ideal output capacitor is calculated as the following equation:
VCOUT = I (V) 8 FOSC COUT
........... (4)
VIN IQ1
Q1
For the applications using bulk capacitors, the VCOUT is much smaller than the VESR and can be ignored. Therefore, the AC peak-to-peak output voltage (VOUT ) is shown as
VOUT
IL
LX
Q2 L
IOUT ESR COUT
below:
VOUT = I ESR (V)
ICOUT
........... (5)
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
15
www.anpec.com.tw
APW7145
Application Information (Cont.)
Output Capacitor Selection (Cont.) For the applications using ceramic capacitors, the VESR is much smaller than the V COUT and can be ignored. Therefore, the AC peak-to-peak output voltage (VOUT ) is close to VCOUT. The load transient requirements are the function of the slew rate (di/dt) and disengaged\the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. An aluminum electrolytic capacitor' ESR value is related to the case size with lower s ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies permit the use of a smaller inductor for the same amount of inductor ripple current. However, this is at the expense of efficiency due to an increase in MOSFET gate charge losses. The equation (2) shows that the inductance value has a direct effect on ripple current. Accepting larger values of ripple current allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is I 0.4 IOUT(MAX). Please be noticed that the maximum ripple current occurs at the maximum input voltage. The minimum inductance of the inductor is calculated by using the following equation:
Compensation Network
5
VOUT *(VIN - VOUT ) 1.2 500000 *L *VIN L VOUT *(VIN - VOUT ) 600000 *VIN (H)
........... (6)
where VIN = VIN(MAX)
Layout Consideration In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In general, interconnecting impedance should be minimized by using short and wide printed circuit traces. Signal and power grounds are to be kept separating and finally combined using ground plane construction or single point grounding. Figure 2 illustrates the layout, with bold lines indicating high current paths. Components along the bold lines should be placed close together. Below is a checklist for your layout: 1. Firstly, to initial the layout by placing the power components. Orient the power circuitry to achieve a clean power flow path. If possible, make all the connections on one side of the PCB with wide and copper filled areas.
+ VIN -
1
2 C1 LX LX 9 7 L1
NC VIN
6
+
C 2 Load VOUT
EN U1 APW7145 COMP
PGND FB
8 4 R1
-
R3 C3 AGND 3
R2
C4(Optional)
Feedback Divider
Figure 2. Current Path Diagram
2. In Figure 2, the loops with same color bold lines conduct high slew rate current. These interconnecting impedances should be minimized by using wide and short printed circuit traces.
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
16
www.anpec.com.tw
APW7145
Application Information (Cont.)
Layout Consideration (Cont.) 3. Keep the sensitive small signal nodes (FB and COMP) away from switching nodes (LX or others) on the PCB. Therefore, place the feedback divider and the feedback compensation network close to the IC to avoid switching noise. Connect the ground of feedback divider directly to the AGND pin of the IC using a dedicated ground trace. 4. Place the decoupling ceramic capacitor C1 near the VIN as close as possible. Use a wide power ground plane to connect the C1 and C2 to provide a low impedance path between the components for large and high slew rate current.
VIN C1 4
5 4
Ground C2
VOUT
APW7145 SOP-8P 5 6 7 8
For dissipating heat
APW7145 DFN4x4
6 7 8
For dissipating heat
Figure 3. Recommended Layout Diagram
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
2 3
3 2
VIN
C1
1 VLX L1 Ground
Ground
C2
VOUT
1 VLX L1
Ground
17
www.anpec.com.tw
APW7145
Package Information
SOP-8P
D SEE VIEW A D1 THERMAL PAD E2 E1
E
e
b
h X 45
c
0.25 GAUGE PLANE SEATING PLANE VIEW A
0
A2 A1
A
L
S Y M B O L A A1 A2 b c D D1 E E1 E2 e h L 0
SOP-8P MILLIMETERS MIN. MAX. 1.60 0.00 1.25 0.31 0.17 4.80 2.25 5.80 3.80 2.00 1.27 BSC 0.25 0.40 0o 0.50 1.27 8o 0.010 0.016 0o 0.51 0.25 5.00 3.50 6.20 4.00 3.00 0.15 0.000 0.049 0.012 0.007 0.189 0.098 0.228 0.150 0.079 0.050 BSC 0.020 0.050 8o 0.020 0.010 0.197 0.138 0.244 0.157 0.118 MIN. INCHES MAX. 0.063 0.006
Note : 1. Follow JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
18
www.anpec.com.tw
APW7145
Package Information
DFN4x4-8
D A
E
Pin 1
D2
A1 A3
e S Y M B O L A A1 A3 b D D2 E E2 e L K 0.40 0.20 0.25 3.90 3.10 3.90 2.40 0.80 BSC 0.60 DFN4x4-8 MILLIMETERS MIN. 0.80 0.00 0.20 REF 0.35 4.10 3.30 4.10 2.60 MAX. 1.00 0.05 MIN. 0.031 0.000 0.008 REF 0.010 0.154 0.122 0.154 0.094 0.014 0.161 0.130 0.161 0.102 INCHES MAX. 0.039 0.002
LK
E2
Pin 1 Corner
0.031 BSC 0.016 0.008 0.024
Note : 1. Followed from JEDEC MO-229 VGGB.
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
19
b
www.anpec.com.tw
APW7145
Carrier Tape & Reel Dimensions
OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B
d
Application
A 330.0O .00 2
H 50 MIN. P1 8.0O .10 0 H 50 MIN. P1 8.0O .10 0
H A
T1
T1 12.4+2.00 -0.00 P2 2.0O .05 0 T1 12.4+2.00 -0.00 P2 2.0O .05 0
C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00 C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00
d 1.5 MIN. D1 1.5 MIN. d 1.5 MIN. D1 1.5 MIN.
D 20.2 MIN. T 0.6+0.00 -0.40 D 20.2 MIN. T 0.6+0.00 -0.40
W 12.0O .30 0 A0 6.40O .20 0 W 12.0O .30 0 A0 4.30O .20 0
E1 1.75O .10 0 B0 5.20O .20 0 E1 1.75O .10 0 B0 4.30O .20 0
W
F 5.5O .05 0 K0 2.10O .20 0 F 5.5O .05 0 K0 1.30O .20 0
SOP-8P
P0 4.0O .10 0
Application
A 330.0O .00 2
DFN4x4-8
P0 4.0O .10 0
(mm)
Devices Per Unit
Package Type SOP-8P DFN4x4-8 Unit Tape & Reel Tape & Reel Quantity 2500 3000
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
20
www.anpec.com.tw
APW7145
Taping Direction Information
SOP-8P
USER DIRECTION OF FEED
DFN4x4-8
USER DIRECTION OF FEED
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
21
www.anpec.com.tw
APW7145
Classification Profile
Classification Reflow Profiles
Profile Feature Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak (Tp)* package body Temperature Sn-Pb Eutectic Assembly 100 C 150 C 60-120 seconds 3 C/second max. 183 C 60-150 seconds See Classification Temp in table 1 20** seconds 6 C/second max. 6 minutes max. Pb-Free Assembly 150 C 200 C 60-120 seconds 3C/second max. 217 C 60-150 seconds See Classification Temp in table 2 30** seconds 6 C/second max. 8 minutes max.
Time (tP)** within 5C of the specified classification temperature (Tc) Average ramp-down rate (Tp to Tsmax) Time 25C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009 22 www.anpec.com.tw
APW7145
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process - Classification Temperatures (Tc) Package Thickness <2.5 mm 2.5 mm
3
Volume mm <350 235 C 220 C
3
Volume mm 350 220 C 220 C
3
3
Table 2. Pb-free Process - Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm - 2.5 mm 2.5 mm Volume mm <350 260 C 260 C 250 C Volume mm 350-2000 260 C 250 C 245 C Volume mm >2000 260 C 245 C 245 C
3
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TCT ESD Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD 78 Description 5 Sec, 245C 1000 Hrs, Bias @ 125C 168 Hrs, 100%RH, 2atm, 121C 500 Cycles, -65C~150C VHBMU2KV, VMMU200V 10ms, 1trU 100mA
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838
Copyright (c) ANPEC Electronics Corp. Rev. A.4- Mar., 2009
23
www.anpec.com.tw

▲Up To Search▲

Price & Availability of APW714509

	To Download APW714509 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .